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2.3. Instantiating the protocol checker modules

The protocol checker modules contain a port list. Connect the ACE or ACE-Lite module ports to the corresponding signals in your design.

See Example Verilog file listing for ACE protocol checker instantiation for an example that shows how the module is instantiated in a top-level Verilog file.

See ARM publications for the specifications that describe the ACE or ACE-Lite signals.

The low-power interface signals of the AXI interface are defined as weak pull-up and you must tie them LOW. They are named:

CSYSREQ

For the low-power request signal.

CSYSACK

For the low-power request acknowledgement signal.

CACTIVE

For the clock active signal.

The SystemVerilog files contain checks for user-configurable sideband signals. You must tie these signals LOW.

This section describes:

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