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A.1. RDATA stable failure

Figure A.1 shows the timing diagram for a failure of the AXI_ERRS_RDATA_STABLE check.

Figure A.1. RDATA stable failure

Figure A.1. RDATA stable failure

RDATA changes at T7 when RVALID is HIGH and RREADY is LOW. The protocol checker samples the change at T8.

Example A.1 shows the protocol checker transcript for this failure.

# Loading sv_std.std
# Loading work.avip_testbench
# Loading work.Axi4PC
# Loading work.BaseClk
# do startup.do 
# AXI4_INFO: Running Axi4PC_ace $State
# ** Error: AXI4_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY LOW.
     Spec: section 3.1, and figure 3-1 on page 3-2.
# Time: 1050 ns Started: 950 ns Scope: avip_testbench.uAxi4PC.axi4_errs_rdata_stable File: ../Axi4PC.sv
     Line: 2595 Expr: $stable(RDATA|~RdataMask)
# ** Note: $finish    : stim.svh(84)
# Time: 3960 ns  Iteration: 1  Instance: /avip_testbench

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