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1.2. Tools

The protocol checkers are written in SystemVerilog. SystemVerilog is a Hardware Description and Verification Language (HDVL) standard that extends the established Verilog language. SystemVerilog was developed to improve productivity in the design of large gate count, IP-based, bus-intensive chips. SystemVerilog is targeted at the chip implementation and verification flow, with links to the system level design flow.

Note

The version of System Verilog supported is IEEE 1800-2005.

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