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Appendix D. Revisions

This appendix describes the technical changes between released issues of this book.

Table D.1. Issue A

First release


Table D.2. Differences between issue A and issue B

Updated daughterboard memory map figure.

Updated daughterboard peripheral memory map table.

Figure 3.1 and Table 3.1.

All revisions

Updated table title.

Table 3.4.All revisions
Added new table to document.Table 3.2.All revisions
Updated default value of HSBM (CLK).Table 2.8.All revisions

Shortened configuration chapter. Information is now in a new document called Versatile™ Express Configuration Technical Reference Manual. See Additional reading.

Added information about custom motherboard.

Configuration architecture.

All revisions

Added new documents to Additional reading:

  • Versatile™ Express Configuration Technical Reference Manual

  • LogicTile Express 13MG Technical Reference Manual.

Additional reading.All revisions
Updated PLL settings register description.Figure 3.14 and Table 3.16.All revisions
Added Energy Meter section.Energy meter.All revisions

Replaced PL310 L2 cache controller with integrated L2 cache controller in the Cortex-A15 MPCore cluster.

Figure 2.2.All revisions

Updated description of Cortex-A15 L2 controller.

Cortex-A15 L2 cache controller.All revisions

Table D.3. Differences between issue B and issue C
Updated address offset range for CPU 0 PTM.Table 3.4.All revisions

Table D.4. Differences between issue C and issue D
Updated interrupt table.Table 2.10.All revisions

Table D.5. Differences between issue D and issue E
Updated introduction to daughterboard memory map section.Daughterboard memory map.All revisions
Corrected typographical error in daughterboard memory map.Table 3.1.All revisions

Table D.6. Differences between issue E and issue F

Corrected memory test chip peripheral areas of memory maps.

Overview of daughterboard memory map.

Overview of the memory map for the on-chip peripherals.

All revisions

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