This appendix describes the technical changes between released issues of this book.
Change | Location | Affects |
---|---|---|
Updated daughterboard memory map figure. Updated daughterboard peripheral memory map table. | Figure 3.1 and Table 3.1. | All revisions |
Updated table title. | Table 3.4. | All revisions |
Added new table to document. | Table 3.2. | All revisions |
Updated default value of HSBM (CLK). | Table 2.8. | All revisions |
Shortened configuration chapter. Information is now in a new document called Versatile™ Express Configuration Technical Reference Manual. See Additional reading. Added information about custom motherboard. | All revisions | |
Added new documents to Additional reading:
| Additional reading. | All revisions |
Updated PLL settings register description. | Figure 3.14 and Table 3.16. | All revisions |
Added Energy Meter section. | Energy meter. | All revisions |
Replaced PL310 L2 cache controller with integrated L2 cache controller in the Cortex-A15 MPCore cluster. | Figure 2.2. | All revisions |
Updated description of Cortex-A15 L2 controller. | Cortex-A15 L2 cache controller. | All revisions |
Change | Location | Affects |
---|---|---|
Updated address offset range for CPU 0 PTM. | Table 3.4. | All revisions |
Change | Location | Affects |
---|---|---|
Updated interrupt table. | Table 2.10. | All revisions |
Change | Location | Affects |
---|---|---|
Updated introduction to daughterboard memory map section. | Daughterboard memory map. | All revisions |
Corrected typographical error in daughterboard memory map. | Table 3.1. | All revisions |
Change | Location | Affects |
---|---|---|
Corrected memory test chip peripheral areas of memory maps. | All revisions |