Ignore this section if caches are not present in your implementation.
This section describes the optional cache maintenance registers in a Cortex-M7 device. These registers control the data and instruction cache.
The operations supported for the instruction cache and data cache are:
Enable or disable a cache.
Invalidate a cache.
Clean a cache.
The cache maintenance operations are only accessible by privileged loads and stores. Unprivileged accesses to these registers always generate a BusFault.
Instruction cache invalidate all to the Point of Unification (PoU)[a]
Instruction cache invalidate by address to the PoU[a]
Data cache invalidate by address to the Point of Coherency (PoC)[b]
Data cache invalidate by set/way
Data cache clean by address to the PoU[a]
|Data cache clean by address to the PoC[b]|
Data cache clean by set/way
Data cache clean and invalidate by address to the PoC[b]
Data cache clean and invalidate by set/way
The BPIALL register is not implemented
[a] Cache maintenance operations by PoU can be used to synchronize data between the Cortex-M7 data and instruction Caches, for example when the software uses self-modifying code.
[b] Cache maintenance operations by PoC can be used to synchronize data between the Cortex-M7 data cache and an external agent such as a system DMA.