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4.1. About the Cortex-M0+ peripherals

The address map of the Private Peripheral Bus (PPB) is:

Table 4.1. Core peripheral register regions
AddressCore peripheralDescription
0xE000E008-0xE000E00FSystem Control BlockTable 4.9
0xE000E010-0xE000E01FReserved-
0xE000E010-0xE000E01FSysTick[a]Table 4.19
0xE000E100-0xE000E4EFNested Vectored Interrupt ControllerTable 4.2
0xE000ED00-0xE000ED3FSystem Control BlockTable 4.9
0xE000ED90MPU Type Register
RAZ

Indicates no MPU is implemented [b]

non-zero
0xE000ED94-0xE000EDB8Memory Protection Unit[c]Table 4.25
0xE000EF00-0xE000EF03Nested Vectored Interrupt ControllerTable 4.2

[a] The system timer is an optional peripheral.

[b] Software can read the MPU Type Register at 0xE000ED90 to test for the presence of a Memory Protection Unit (MPU).

[c] The Memory Protection Unit is an optional peripheral.


In register descriptions:

  • the register type is described as follows:

    RW

    Read and write.

    RO

    Read-only.

    WO

    Write-only.

  • the required privilege applies only to some optional peripherals. It gives the privilege level required to access the register, as follows:

    Privileged

    Only privileged software can access the register.

    Unprivileged

    Both unprivileged and privileged software can access the register.

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