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4.5. Memory Protection Unit

This section describes the optional Memory Protection Unit (MPU).

The MPU can divide the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:

  • independent attribute settings for each region

  • overlapping regions

  • export of memory attributes to the system.

The memory attributes affect the behavior of memory accesses to the region. The Cortex-M0+ MPU defines:

  • eight separate memory regions, 0-7

  • a background region.

When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.

The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only.

The Cortex-M0+ MPU memory map is unified. This means instruction accesses and data accesses have the same region settings.

If a program accesses a memory location that is prohibited by the MPU, the processor generates a HardFault exception. In an OS environment, the kernel can update the MPU region settings dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.

Configuration of MPU regions is based on memory types, see Memory regions, types and attributes.

Table 4.24 shows the possible MPU region attributes. These include Shareability and cache behavior attributes that are not relevant to most microcontroller implementations. See MPU configuration for a microcontroller for guidelines for programming such an implementation.

Table 4.24. Memory attributes summary
Memory typeShareabilityOther attributesDescription
Strongly- ordered--All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared.
DeviceShared-Memory-mapped peripherals that several processors share.
 Non-shared-Memory-mapped peripherals that only a single processor uses.
NormalSharedNon-cacheable Write-through Cacheable Write-back CacheableNormal memory that is shared between several processors.
 Non-sharedNon-cacheable Write-through Cacheable Write-back CacheableNormal memory that only a single processor uses.

Use the MPU registers to define the MPU regions and their attributes. Table 4.25 shows the MPU registers.

Table 4.25. MPU registers summary
AddressName Type

Reset value

Description
0xE000ED90MPU_TYPERO

0x00000800

MPU Type Register
0xE000ED94MPU_CTRLRW0x00000000MPU Control Register
0xE000ED98MPU_RNRRW0x00000000MPU Region Number Register
0xE000ED9CMPU_RBARRW0x00000000MPU Region Base Address Register
0xE000EDA0MPU_RASRRW0x00000000MPU Region Attribute and Size Register

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