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4.3.5. Application Interrupt and Reset Control Register

The AIRCR provides endian status for data accesses and reset control of the system. See the register summary in Table 4.9 and Table 4.13 for its attributes.

To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor ignores the write.

The bit assignments are:

Table 4.13. AIRCR bit assignments
BitsNameTypeFunction
[31:16]

Read: Reserved

Write: VECTKEY

RW

Register key:

Reads as Unknown

On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.

[15]ENDIANNESSRO

Data endianness implemented:

0 = little-endian

1 = big-endian.

[14:3]--Reserved
[2]SYSRESETREQWO

System reset request:

0 = no effect

1 = requests a system level reset.

This bit reads as 0.

[1]VECTCLRACTIVEWOReserved for debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.
[0]--Reserved.

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