The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that have configurable priority.

SHPR2-SHPR3 are word accessible. See the register summary in Table 4.9 for their attributes.

To access to the system exception priority level using CMSIS, use the following CMSIS functions:

The input parameter IRQn is the IRQ number, see Table 2.11 for more information.

The system fault handlers, and the priority field and register for each handler are:

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field, and bits[5:0] read as zero and ignore writes.

System Handler Priority Register 2

The bit assignments are:

Table 4.17. SHPR2 register bit assignments

Bits	Name	Function
[31:24]	PRI_11	Priority of system handler 11, SVCall
[23:0]	-	Reserved

System Handler Priority Register 3

The bit assignments are:

Table 4.18. SHPR3 register bit assignments

Bits	Name	Function
[31:24]	PRI_15	Priority of system handler 15, SysTick exception[a]
[23:16]	PRI_14	Priority of system handler 14, PendSV
[15:0]	-	Reserved
[a] This is Reserved when the SysTick timer is not implemented.