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4.3.8. System Handler Priority Registers

The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that have configurable priority.

SHPR2-SHPR3 are word accessible. See the register summary in Table 4.9 for their attributes.

To access to the system exception priority level using CMSIS, use the following CMSIS functions:

  • uint32_t NVIC_GetPriority(IRQn_Type IRQn)

  • void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

The input parameter IRQn is the IRQ number, see Table 2.11 for more information.

The system fault handlers, and the priority field and register for each handler are:

Table 4.16. System fault handler priority fields
HandlerFieldRegister description
SVCallPRI_11System Handler Priority Register 2
PendSVPRI_14System Handler Priority Register 3

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field, and bits[5:0] read as zero and ignore writes.

System Handler Priority Register 2

The bit assignments are:

Table 4.17. SHPR2 register bit assignments
[31:24]PRI_11Priority of system handler 11, SVCall

System Handler Priority Register 3

The bit assignments are:

Table 4.18. SHPR3 register bit assignments
[31:24]PRI_15Priority of system handler 15, SysTick exception[a]
[23:16]PRI_14Priority of system handler 14, PendSV

[a] This is Reserved when the SysTick timer is not implemented.

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