When enabled, the system timer counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR on the next clock cycle, then decrements on subsequent clock cycles. Writing a value of zero to the SYST_RVR disables the counter on the next wrap. When the counter transitions to zero, the COUNTFLAG status bit is set to 1. Reading SYST_CSR clears the COUNTFLAG bit to 0.Writing to the SYST_CVR clears the register and the COUNTFLAG status bit to 0. The write does not trigger the SysTick exception logic. Reading the register returns its value at the time it is accessed.
Note
When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
| Address | Name | Type | Required privilege | Reset value | Description |
|---|---|---|---|---|---|
0xE000E010 | SYST_CSR | RW | Privileged | 0x00000000 | SysTick Control and Status Register |
0xE000E014 | SYST_RVR | RW | Privileged | Unknown | SysTick Reload Value Register |
0xE000E018 | SYST_CVR | RW | Privileged | Unknown | SysTick Current Value Register |
0xE000E01C | SYST_CALIB | RO | Privileged | Implementation Defined [a] | SysTick Calibration Value Register |
[a] SysTick calibration value. | |||||