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1.1. About the Cortex-M0+ processor and core peripherals

The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

  • a simple architecture that is easy to learn and program

  • ultra-low power, energy-efficient operation

  • excellent code density

  • deterministic, high-performance interrupt handling

  • upward compatibility with Cortex-M processor family

  • platform security robustness, with optional integrated Memory Protection Unit (MPU).

Figure 1.1. Cortex-M0+ implementation

Figure 1.1. Cortex-M0+ implementation

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including either:

  • a single-cycle multiplier, in designs optimized for high performance

  • a 32-cycle multiplier, in designs optimized for low area.

The Cortex-M0+ processor implements the ARMv6-M architecture, that is based on the 16-bit Thumb® instruction set and includes Thumb-2 technology. This provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than 8-bit and 16-bit microcontrollers.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

  • includes a Non-Maskable Interrupt (NMI)

  • provides zero jitter interrupt option

  • provides four interrupt priority levels.

The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart load-multiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes. Optionally, sleep mode support can include a deep sleep function that enables the entire device to be rapidly powered down.

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