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#### Syntax

```ADCS   {`Rd`,} `Rn`, `Rm`
```
```ADD{S} {`Rd`,} `Rn`, `<Rm|#imm>`
```
```RSBS   {`Rd`,} `Rn`, `Rm`, `#0`
```
```SBCS   {`Rd`,} `Rn`, `Rm`
```
```SUB{S} {`Rd`,} `Rn`, `<Rm|#imm>`
```

Where:

`S`

Causes an `ADD` or `SUB` instruction to update flags

`Rd`

Specifies the result register

`Rn`

Specifies the first source register

`Rm`

Specifies the second source register

`imm`

Specifies a constant immediate value.

When the optional `Rd` register specifier is omitted, it is assumed to take the same value as `Rn`, for example `ADDS R1,R2` is identical to `ADDS R1,R1,R2`.

#### Operation

The `ADCS` instruction adds the value in `Rn `to the value in `Rm`, adding another one if the carry flag is set, places the result in the register specified by `Rd` and updates the N, Z, C, and V flags.

The `ADD` instruction adds the value in `Rn` to the value in `Rm` or an immediate value specified by `imm` and places the result in the register specified by `Rd`.

The `ADDS` instruction performs the same operation as `ADD` and also updates the N, Z, C and V flags.

The `RSBS` instruction subtracts the value in `Rn` from zero, producing the arithmetic negative of the value, and places the result in the register specified by Rd and updates the N, Z, C and V flags.

The `SBCS` instruction subtracts the value of `Rm` from the value in `Rn`, deducts another one if the carry flag is set. It places the result in the register specified by Rd and updates the N, Z, C and V flags.

The `SUB` instruction subtracts the value in `Rm` or the immediate specified by `imm`. It places the result in the register specified by `Rd`.

The `SUBS` instruction performs the same operation as `SUB` and also updates the N, Z, C and V flags.

Use `ADC` and `SBC` to synthesize multiword arithmetic, see Examples.

#### Restrictions

Table 3.7 lists the legal combinations of register specifiers and immediate values that can be used with each instruction.

InstructionRdRnRmimmRestrictions
`ADCS`R0-R7R0-R7R0-R7-

`Rd` and `Rn` must specify the same register.

`ADD`R0-R15R0-R15R0-PC-

`Rd` and `Rn` must specify the same register.

`Rn` and `Rm` must not both specify PC.

R0-R7SP or PC-0-1020

Immediate value must be an integer multiple of four.

SPSP-0-508

Immediate value must be an integer multiple of four.

`ADDS`R0-R7R0-R7-0-7-
R0-R7R0-R7-0-255

`Rd` and `Rn` must specify the same register.

R0-R7R0-R7R0-R7--
`RSBS`R0-R7R0-R7---
`SBCS`R0-R7R0-R7R0-R7-

`Rd` and `Rn` must specify the same register.

`SUB`SPSP-0-508

Immediate value must be an integer multiple of four.

`SUBS`R0-R7R0-R7-0-7-
R0-R7R0-R7-0-255

`Rd` and `Rn` must specify the same register.

R0-R7R0-R7R0-R7--

#### Examples

Example 3.1 shows two instructions that add a 64-bit integer contained in R0 and R1 to another 64-bit integer contained in R2 and R3, and place the result in R0 and `R1`.

```    ADDS    R0, R0, R2    ; add the least significant words
ADCS    R1, R1, R3    ; add the most significant words with carry
```

Multiword values do not have to use consecutive registers. Example 3.2 shows instructions that subtract a 96-bit integer contained in R1, R2, and R3 from another contained in R4, R5, and R6. The example stores the result in R4, R5, and R6.

```    SUBS    R4, R4, R1    ; subtract the least significant words
SBCS    R5, R5, R2    ; subtract the middle words with carry
SBCS    R6, R6, R3    ; subtract the most significant words with carry
```

Example 3.3 shows the `RSBS` instruction used to perform a 1's complement of a single register.

```    RSBS    R7, R7, #0    ; subtract R7 from zero
```