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Table 3.10 shows the remaining Cortex-M0+ instructions:
Mnemonic | Brief description | See |
---|---|---|
BKPT | Breakpoint | BKPT |
CPSID | Change Processor State, Disable Interrupts | CPS |
CPSIE | Change Processor State, Enable Interrupts | CPS |
DMB | Data Memory Barrier | DMB |
DSB | Data Synchronization Barrier | DSB |
ISB | Instruction Synchronization Barrier | ISB |
MRS | Move from special register to register | MRS |
MSR | Move from register to special register | MSR |
NOP | No Operation | NOP |
SEV | Send Event | SEV |
SVC | Supervisor Call | SVC |
WFE | Wait For Event | WFE |
WFI
| Wait For Interrupt | WFI |