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4.2.2. Interrupt Clear-Enable Register

The NVIC_ICER disables interrupts, and show which interrupts are enabled. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

Table 4.4. NVIC_ICER bit assignments
BitsNameFunction
[31:0]CLRENA

Interrupt clear-enable bits.

Write:

0 = no effect.

1 = disable interrupt.

Read:

0 = interrupt disabled.

1 = interrupt enabled.


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