You copied the Doc URL to your clipboard.

4.2.5. Interrupt Priority Registers

The NVIC_IPR0-NVIC_IPR7 registers provide an 8-bit priority field for each interrupt. These registers are only word-accessible. See the register summary in Table 4.2 for their attributes. Each register holds four priority fields as shown:

Table 4.7. NVIC_IPRx bit assignments
Bits NameFunction
[31:24] Priority, byte offset 3

Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:6] of each field, bits [5:0] read as zero and ignore writes. This means writing 255 to a priority register saves value 192 to the register.

[23:16] Priority, byte offset 2
[15:8] Priority, byte offset 1
[7:0] Priority, byte offset 0

See NVIC usage hints and tips for more information about the access to the interrupt priority array, which provides the software view of the interrupt priorities.

Find the NVIC_IPR number and byte offset for interrupt M as follows:

  • the corresponding NVIC_IPR number, N, is given by N = N DIV 4

  • the byte offset of the required Priority field in this register is M MOD 4, where:

    • Byte offset 0 refers to register bits[7:0].

    • Byte offset 1 refers to register bits[15:8].

    • Byte offset 2 refers to register bits[23:16].

    • Byte offset 3 refers to register bits[31:24].

Was this page helpful? Yes No