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4.2.3. Interrupt Set-Pending Register

The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. See the register summary in Table 4.2 for the register attributes.

The bit assignments are:

Table 4.5. NVIC_ISPR bit assignments

Interrupt set-pending bits.


0 = no effect.

1 = changes interrupt state to pending.


0 = interrupt is not pending.

1 = interrupt is pending.


Writing 1 to the NVIC_ISPR bit corresponding to:

  • An interrupt that is pending has no effect.

  • A disabled interrupt sets the state of that interrupt to pending.

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