The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. See the register summary in Table 4.2 for the register attributes.
The bit assignments are:
Interrupt set-pending bits.
0 = no effect.
1 = changes interrupt state to pending.
0 = interrupt is not pending.
1 = interrupt is pending.
Writing 1 to the NVIC_ISPR bit corresponding to:
An interrupt that is pending has no effect.
A disabled interrupt sets the state of that interrupt to pending.