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4.2.6. Level-sensitive and pulse interrupts

The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.

When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Hardware and software control of interrupts. For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.

The details of which interrupts are level-sensitive and which are pulsed are specific to your device.

Hardware and software control of interrupts

The Cortex-M0+ processor latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:

  • The NVIC detects that the interrupt signal is asserted and the corresponding interrupt is not active.

  • The NVIC detects a rising edge on the interrupt signal.

  • Software writes to the corresponding interrupt set-pending register bit, see Interrupt Set-Pending Register.

A pending interrupt remains pending until one of the following:

  • The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:

    • For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, that might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.

    • For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, that might cause the processor to immediately re-enter the ISR.

      If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive.

  • Software writes to the corresponding interrupt clear-pending register bit.

    For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive.

    For a pulse interrupt, the state of the interrupt changes to:

    • Inactive, if the state was pending.

    • Active, if the state was active and pending.

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