Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers.
An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
Before programming the optional VTOR to relocate the vector table, you must set up entries in the new vector table for all exceptions that might be taken, such as NMI, HardFault and enabled interrupts. For more information, see Vector Table Offset Register.
Software uses the
CPSIE i and
CPSID i instructions
to enable and disable interrupts. CMSIS provides the following intrinsic
functions for these instructions:
void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts
In addition, CMSIS provides a number of functions for NVIC control, including:
|CMSIS interrupt control function||Description|
|Return true (1) if IRQn is pending.|
|Set IRQn pending.|
|Clear IRQn pending status.|
|Set priority for IRQn.|
|Read priority of IRQn.|
|Request a system reset.|