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3.6.1. B, BL, BX, and BLX

Branch instructions.


B{cond} label
BL label



Is an optional condition code, see Conditional execution.


Is a PC-relative expression. See PC‑relative expressions.


Is a register providing the address to branch to.


All these instructions cause a branch to the address indicated by label or contained in the register specified by Rm. In addition:

  • The BL and BLX instructions write the address of the next instruction to LR, the link register R14.

  • The BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.

BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable for use by a subsequent POP {PC} or BX instruction to perform a successful return branch.

Table 3.9 shows the ranges for the various branch instructions.

Table 3.9. Branch ranges
Instruction Branch range
B label −2 KB to +2 KB.
B cond label −256 bytes to +254 bytes.
BL label −16 MB to +16 MB.
BX Rm Any value in register.
BLX Rm Any value in register.


In these instructions:

  • Do not use SP or PC in the BX or BLX instruction.

  • For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update the EPSR T-bit and is discarded from the target address.


Bcondis the only conditional instruction on the Cortex-M0+ processor.

Condition flags

These instructions do not change the flags.


    B      loopA  ; Branch to loopA
    BL     funC   ; Branch with link (Call) to function funC, return address
                  ; stored in LR
    BX     LR     ; Return from function call
    BLX    R0     ; Branch with link and exchange (Call) to a address stored
                  ; in R0
    BEQ    labelD ; Conditionally branch to labelD if last flag setting
                  ; instruction set the Z flag, else do not branch.

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