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The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises:
All of the 16-bit Thumb instructions from ARMv7-M excluding
CBZ
,CBNZ
andIT
.The 32-bit Thumb instructions
BL
,DMB
,DSB
,ISB
,MRS
andMSR
.
Table 3.1 lists the supported instructions.
Note
In Table 3.1:
Angle brackets, <>, enclose alternative forms of the operand.
Braces, {}, enclose optional operands and mnemonic parts.
The Operands column is not exhaustive.
For more information on the instructions and operands, see the instruction descriptions.
Mnemonic | Operands | Brief description | Flags | Page |
---|---|---|---|---|
ADCS |
| Add with Carry | N,Z,C,V | ADC, ADD, RSB, SBC, and SUB |
ADD{S} |
| Add | N,Z,C,V | ADC, ADD, RSB, SBC, and SUB |
ADR |
| PC-relative Address to Register | - | ADR |
ANDS |
| Bitwise AND | N,Z | ADC, ADD, RSB, SBC, and SUB |
ASRS |
| Arithmetic Shift Right | N,Z,C | ASR, LSL, LSR, and ROR |
B{cc} |
| Branch {conditionally} | - | B, BL, BX, and BLX |
BICS |
| Bit Clear | N,Z | AND, ORR, EOR, and BIC |
BKPT |
| Breakpoint | - | BKPT |
BL |
| Branch with Link | - | B, BL, BX, and BLX |
BLX |
| Branch indirect with Link | - | B, BL, BX, and BLX |
BX |
| Branch indirect | - | B, BL, BX, and BLX |
CMN |
| Compare Negative | N,Z,C,V | CMP and CMN |
CMP |
| Compare | N,Z,C,V | CMP and CMN |
CPSID |
| Change Processor State, Disable Interrupts | - | CPS |
CPSIE |
| Change Processor State, Enable Interrupts | - | CPS |
DMB |
| Data Memory Barrier | - | DMB |
DSB |
| Data Synchronization Barrier | - | DSB |
EORS |
| Exclusive OR | N,Z | AND, ORR, EOR, and BIC |
ISB |
| Instruction Synchronization Barrier | - | ISB |
LDM |
| Load Multiple registers, increment after | - | LDM and STM |
LDR |
| Load Register from PC-relative address | - | Memory access instructions |
LDR |
| Load Register with word | - | Memory access instructions |
LDRB |
| Load Register with byte | - | Memory access instructions |
LDRH |
| Load Register with halfword | - | Memory access instructions |
LDRSB |
| Load Register with signed byte | - | Memory access instructions |
LDRSH |
| Load Register with signed halfword | - | Memory access instructions |
LSLS |
| Logical Shift Left | N,Z,C | ASR, LSL, LSR, and ROR |
LSRS |
| Logical Shift Right | N,Z,C | ASR, LSL, LSR, and ROR |
MOV{S } |
| Move | N,Z | MOV and MVN |
MRS |
| Move to general register from special register | - | MRS |
MSR |
| Move to special register from general register | N,Z,C,V | MSR |
MULS |
| Multiply, 32-bit result | N,Z | MULS |
MVNS |
| Bitwise NOT | N,Z | MOV and MVN |
NOP | - | No Operation | - | NOP |
ORRS |
| Logical OR | N,Z | AND, ORR, EOR, and BIC |
POP |
| Pop registers from stack | - | PUSH and POP |
PUSH |
| Push registers onto stack | - | PUSH and POP |
REV |
| Byte-Reverse word | - | REV, REV16, and REVSH |
REV16
|
| Byte-Reverse packed halfwords | - | REV, REV16, and REVSH |
REVSH |
| Byte-Reverse signed halfword | - | REV, REV16, and REVSH |
RORS |
| Rotate Right | N,Z,C | ASR, LSL, LSR, and ROR |
RSBS |
| Reverse Subtract | N,Z,C,V | ADC, ADD, RSB, SBC, and SUB |
SBCS |
| Subtract with Carry | N,Z,C,V | ADC, ADD, RSB, SBC, and SUB |
SEV | - | Send Event | - | SEV |
STM |
| Store Multiple registers, increment after | - | LDM and STM |
STR |
| Store Register as word | - | Memory access instructions |
STRB |
| Store Register as byte | - | Memory access instructions |
STRH |
| Store Register as halfword | - | Memory access instructions |
SUB{S} |
| Subtract | N,Z,C,V | ADC, ADD, RSB, SBC, and SUB |
SVC |
| Supervisor Call | - | SVC |
SXTB |
| Sign extend byte | - | SXT and UXT |
SXTH |
| Sign extend halfword | - | SXT and UXT |
TST |
| Logical AND based test | N,Z | TST |
UXTB |
| Zero extend a byte | - | SXT and UXT |
UXTH |
| Zero extend a halfword | - | SXT and UXT |
WFE | - | Wait For Event | - | WFE |
WFI
| - | Wait For Interrupt | - | WFI |