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3.1. Instruction set summary

The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises:

  • All of the 16-bit Thumb instructions from ARMv7-M excluding CBZ, CBNZ and IT.

  • The 32-bit Thumb instructions BL, DMB, DSB, ISB, MRS and MSR.

Table 3.1 lists the supported instructions.


In Table 3.1:

  • Angle brackets, <>, enclose alternative forms of the operand.

  • Braces, {}, enclose optional operands and mnemonic parts.

  • The Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.

Table 3.1. Cortex-M0+ instructions
MnemonicOperandsBrief descriptionFlagsPage
ADCS{Rd,} Rn, RmAdd with CarryN,Z,C,VADC, ADD, RSB, SBC, and SUB
ADD{S}{Rd,} Rn, <Rm|#imm>Add N,Z,C,VADC, ADD, RSB, SBC, and SUB
ADRRd, labelPC-relative Address to Register-ADR
ANDS{Rd,} Rn, RmBitwise ANDN,ZADC, ADD, RSB, SBC, and SUB
ASRS{Rd,} Rm, <Rs|#imm>Arithmetic Shift RightN,Z,CASR, LSL, LSR, and ROR
B{cc}labelBranch {conditionally}-B, BL, BX, and BLX
BICS{Rd,} Rn, RmBit ClearN,ZAND, ORR, EOR, and BIC
BLlabelBranch with Link-B, BL, BX, and BLX
BLXRmBranch indirect with Link-B, BL, BX, and BLX
BXRmBranch indirect-B, BL, BX, and BLX
CMNRn, RmCompare NegativeN,Z,C,VCMP and CMN
CMPRn, <Rm|#imm>CompareN,Z,C,VCMP and CMN
CPSIDiChange Processor State, Disable Interrupts-CPS
CPSIEiChange Processor State, Enable Interrupts-CPS
DMB-Data Memory Barrier-DMB
DSB-Data Synchronization Barrier-DSB
EORS{Rd,} Rn, RmExclusive ORN,ZAND, ORR, EOR, and BIC
ISB-Instruction Synchronization Barrier-ISB
LDMRn{!}, reglistLoad Multiple registers, increment after-LDM and STM
LDRRt, labelLoad Register from PC-relative address-Memory access instructions
LDRRt, [Rn, <Rm|#imm>]Load Register with word-Memory access instructions
LDRBRt, [Rn, <Rm|#imm>]Load Register with byte-Memory access instructions
LDRHRt, [Rn, <Rm|#imm>]Load Register with halfword-Memory access instructions
LDRSBRt, [Rn, <Rm|#imm>]Load Register with signed byte-Memory access instructions
LDRSHRt, [Rn, <Rm|#imm>]Load Register with signed halfword-Memory access instructions
LSLS{Rd,} Rn, <Rs|#imm>Logical Shift LeftN,Z,CASR, LSL, LSR, and ROR
LSRS{Rd,} Rn, <Rs|#imm>Logical Shift RightN,Z,CASR, LSL, LSR, and ROR
MOV{S}Rd, RmMoveN,ZMOV and MVN
MRSRd, spec_regMove to general register from special register-MRS
MSRspec_reg, RmMove to special register from general registerN,Z,C,VMSR
MULSRd, Rn, RmMultiply, 32-bit resultN,ZMULS
NOP-No Operation-NOP
ORRS{Rd,} Rn, RmLogical ORN,ZAND, ORR, EOR, and BIC
POPreglistPop registers from stack-PUSH and POP
PUSHreglistPush registers onto stack-PUSH and POP
REVRd, RmByte-Reverse word-REV, REV16, and REVSH
REV16Rd, RmByte-Reverse packed halfwords-REV, REV16, and REVSH
REVSHRd, RmByte-Reverse signed halfword-REV, REV16, and REVSH
RORS{Rd,} Rn, RsRotate RightN,Z,CASR, LSL, LSR, and ROR
RSBS{Rd,} Rn, #0Reverse SubtractN,Z,C,VADC, ADD, RSB, SBC, and SUB
SBCS{Rd,} Rn, RmSubtract with CarryN,Z,C,VADC, ADD, RSB, SBC, and SUB
SEV-Send Event-SEV
STMRn!, reglistStore Multiple registers, increment after-LDM and STM
STRRt, [Rn, <Rm|#imm>]Store Register as word-Memory access instructions
STRBRt, [Rn, <Rm|#imm>]Store Register as byte-Memory access instructions
STRHRt, [Rn, <Rm|#imm>]Store Register as halfword-Memory access instructions
SUB{S}{Rd,} Rn, <Rm|#imm>SubtractN,Z,C,VADC, ADD, RSB, SBC, and SUB
SVC#immSupervisor Call-SVC
SXTBRd, Rm Sign extend byte-SXT and UXT
SXTHRd, RmSign extend halfword-SXT and UXT
TSTRn, RmLogical AND based testN,ZTST
UXTBRd, RmZero extend a byte-SXT and UXT
UXTHRd, RmZero extend a halfword-SXT and UXT
WFE-Wait For Event-WFE
WFI-Wait For Interrupt-WFI

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