You copied the Doc URL to your clipboard.

3.7. Miscellaneous instructions

Table 3.10 shows the remaining Cortex-M0+ instructions:

Table 3.10. Miscellaneous instructions
MnemonicBrief descriptionSee
CPSIDChange Processor State, Disable InterruptsCPS.
CPSIEChange Processor State, Enable InterruptsCPS.
DMBData Memory BarrierDMB.
DSBData Synchronization BarrierDSB.
ISBInstruction Synchronization BarrierISB.
MRSMove from special register to registerMRS.
MSRMove from register to special registerMSR.
NOPNo OperationNOP.
SEVSend EventSEV.
SVCSupervisor CallSVC.
WFEWait For EventWFE.
WFIWait For InterruptWFI.