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2.1.3. Core registers

The processor core registers are:

Table 2.2. Core register set summary
NameType [a]

Reset value

Description
R0-R12RWUnknownGeneral-purpose registers.
MSPRWSee descriptionStack Pointer.
PSPRWUnknownStack Pointer.
LRRWUnknownLink Register.
PCRWSee descriptionProgram Counter.
PSRRWUnknown[b]Program Status Register.
APSRRWUnknown Application Program Status Register.
IPSRRO0x00000000Interrupt Program Status Register.
EPSRROUnknown [b] Execution Program Status Register.
PRIMASKRW0x00000000Priority Mask Register.
CONTROLRW0x00000000CONTROL register.

[a] Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.

[b] Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.


General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack Pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:

  • 0 = Main Stack Pointer (MSP). This is the reset value.

  • 1 = Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the LR value is Unknown.

Program Counter

The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, that is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

Program Status Register

The Program Status Register (PSR) combines:

  • Application Program Status Register (APSR).

  • Interrupt Program Status Register (IPSR).

  • Execution Program Status Register (EPSR).

These registers are allocated as mutually exclusive bitfields within the 32-bit PSR. The PSR bit assignments are:

Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:

  • Read all of the registers using PSR with the MRS instruction.

  • Write to the APSR using APSR with the MSR instruction.

The PSR combinations and attributes are:

Table 2.3. PSR register combinations
RegisterTypeCombination
PSRRW[a], [b]APSR, EPSR, and IPSR.
IEPSRROEPSR and IPSR.
IAPSRRW[a]APSR and IPSR.
EAPSRRW[b]APSR and EPSR.

[a] The processor ignores writes to the IPSR bits.

[b] Reads of the EPSR bits return zero, and the processor ignores writes to these bits


See the instruction descriptions MRS and MSR for more information about how to access the program status registers.

Application Program Status Register

The APSR contains the current state of the condition flags, from previous instruction executions. See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.4. APSR bit assignments
BitsNameFunction
[31]N

Negative flag.

[30]Z

Zero flag.

[29]C

Carry or borrow flag.

[28]V

Overflow flag.

[27:0]-Reserved.

See The condition flags for more information about the APSR negative, zero, carry or borrow, and overflow flags.

Interrupt Program Status Register

The IPSR contains the exception number of the current Interrupt Service Routine (ISR). See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.5. IPSR bit assignments
BitsNameFunction
[31:6]-Reserved.
[5:0]Exception number

This is the number of the current exception:

0 = Thread mode.

1 = Reserved.

2 = NMI.

3 = HardFault.

4-10 = Reserved.

11 = SVCall.

12, 13 = Reserved.

14 = PendSV.

15 = SysTick, if implemented[a].

16 = IRQ0.

.

.

47 = IRQ31[b].

48-63 = Reserved.

see Exception types for more information.

[a] If the device does not implement the SysTick timer, exception number 15 is reserved.

[b] The number of functional interrupts is configured by the MCU implementer.


Execution Program Status Register

The EPSR contains the Thumb state bit.

See the register summary in Table 2.2 for the EPSR attributes. The bit assignments are:

Table 2.6. EPSR bit assignments
BitsNameFunction
[31:25]-Reserved.
[24]TThumb state bit.
[23:0]-Reserved.

Attempts by application software to read the EPSR directly using the MRS instruction always return zero. Attempts to write the EPSR using the MSR instruction are ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the cause of the fault. See Exception entry and return. The following can clear the T bit to 0:

  • Instructions BLX, BX and POP{PC}.

  • Restoration from the stacked xPSR value on an exception return.

  • Bit[0] of the vector value on an exception entry.

Attempting to execute instructions when the T bit is 0 results in a HardFault or Lockup. See Lockup for more information.

Interruptible-restartable instructions

The interruptible-restartable instructions are LDM, STM, PUSH, POP and, in 32-cycle multiplier implementations, MULS. When an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning.

Exception mask register

The exception mask register disables the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity.

To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS instruction, to change the value of PRIMASK. See MRS, MSR, and CPS for more information.

Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.7. PRIMASK register bit assignments
BitsNameFunction
[31:1]-Reserved.
[0]PM

Prioritizable interrupt mask:

0 = no effect.

1 = prevents the activation of all exceptions with configurable priority.


CONTROL register

The CONTROL register controls the stack used, and the optional privilege level for software execution, when the processor is in Thread mode. See the register summary in Table 2.2 for its attributes. The bit assignments are:

Table 2.8. CONTROL register bit assignments
BitsNameFunction
[31:2]-Reserved.
[1]SPSEL

Defines the current stack:

0 = MSP is the current stack pointer.

1 = PSP is the current stack pointer.

In Handler mode this bit reads as zero and ignores writes.

[0]nPRIV[a]

Defines the Thread mode privilege level:

0 = Privileged.

1 = Unprivileged.

[a] If the Unprivileged/Privileged extension is not configured, this bit is Reserved, RAZ.


Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register.

In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruction to set the active stack pointer bit to 1, see MRS.

Note

When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See ISB.