The processor core registers are:
|MSP||RW||See description||Stack Pointer.|
|PC||RW||See description||Program Counter.|
|PSR||RW||Unknown[b]||Program Status Register.|
|APSR||RW||Unknown||Application Program Status Register.|
|IPSR||RO||Interrupt Program Status Register.|
|EPSR||RO||Unknown [b]||Execution Program Status Register.|
|PRIMASK||RW||Priority Mask Register.|
[a] Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.
[b] Bit is the T-bit and is loaded from bit of the reset vector.
The Stack Pointer (SP) is register R13. In Thread mode, bit of the CONTROL register indicates the stack pointer to use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
reset, the processor loads the MSP with the value from address
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the LR value is Unknown.
The Program Counter (PC) is register
R15. It contains the current program address. On reset, the processor
loads the PC with the value of the reset vector, that is at address
Bit of the value is loaded into the EPSR T-bit at reset and must
The Program Status Register (PSR) combines:
Application Program Status Register (APSR).
Interrupt Program Status Register (IPSR).
Execution Program Status Register (EPSR).
These registers are allocated as mutually exclusive bitfields within the 32-bit PSR. The PSR bit assignments are:
Access these registers individually or as a combination of
any two or all three registers, using the register name as an argument
MRS instructions. For example:
Read all of the registers using
Write to the APSR using
The PSR combinations and attributes are:
The APSR contains the current state of the condition flags, from previous instruction executions. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Carry or borrow flag.
See The condition flags for more information about the APSR negative, zero, carry or borrow, and overflow flags.
The IPSR contains the exception number of the current Interrupt Service Routine (ISR). See the register summary in Table 2.2 for its attributes. The bit assignments are:
This is the number of the current exception:
0 = Thread mode.
1 = Reserved.
2 = NMI.
3 = HardFault.
4-10 = Reserved.
11 = SVCall.
12, 13 = Reserved.
14 = PendSV.
15 = SysTick, if implemented[a].
16 = IRQ0.
47 = IRQ31[b].
48-63 = Reserved.
see Exception types for more information.
[a] If the device does not implement the SysTick timer, exception number 15 is reserved.
[b] The number of functional interrupts is configured by the MCU implementer.
The EPSR contains the Thumb state bit.
See the register summary in Table 2.2 for the EPSR attributes. The bit assignments are:
|||T||Thumb state bit.|
Attempts by application software to read the EPSR directly
MRS instruction always return zero. Attempts
to write the EPSR using the
MSR instruction are ignored.
Fault handlers can examine the EPSR value in the stacked PSR to
determine the cause of the fault. See Exception entry and return. The following can clear the T bit to
Restoration from the stacked xPSR value on an exception return.
Bit of the vector value on an exception entry.
Attempting to execute instructions when the T bit is 0 results in a HardFault or Lockup. See Lockup for more information.
The interruptible-restartable instructions are
in 32-cycle multiplier implementations,
an interrupt occurs during the execution of one of these instructions,
the processor abandons execution of the instruction. After servicing
the interrupt, the processor restarts execution of the instruction
from the beginning.
The exception mask register disables the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity.
The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Prioritizable interrupt mask:
0 = no effect.
1 = prevents the activation of all exceptions with configurable priority.
The CONTROL register controls the stack used, and the optional privilege level for software execution, when the processor is in Thread mode. See the register summary in Table 2.2 for its attributes. The bit assignments are:
Defines the current stack:
0 = MSP is the current stack pointer.
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Defines the Thread mode privilege level:
0 = Privileged.
1 = Unprivileged.
[a] If the Unprivileged/Privileged extension is not configured, this bit is Reserved, RAZ.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack
pointer used in Thread mode to the PSP, use the
to set the active stack pointer bit to 1, see MRS.
When changing the stack pointer, software must use an
immediately after the
MSR instruction. This ensures
that instructions after the
ISB execute using the new
stack pointer. See ISB.