The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. See the register summary in Table 4.25 for its attributes.
The bit assignments are:
Instruction access disable bit:
0 = instruction fetches enabled.1 = instruction fetches disabled.
|[26:24]||AP||Access permission field, see Table 4.33.|
Shareable bit, see Table 4.32.
Cacheable bit, see Table 4.32.
Bufferable bit, see Table 4.32.
Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled.
1 = corresponding sub-region is disabled.
See Subregions for more information.
|[5:1]||SIZE||Specifies the size of the MPU region. The minimum permitted value is 7 (b00111). See SIZE field values for more information.|
|||ENABLE||Region enable bit.[a]|
[a] The region enable bit of all regions is reset to 0. This enables you to only program regions you want enabled.
For information about access permission, see MPU access permission attributes.
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR, as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 256B, corresponding to a SIZE value of 7. Table 4.31 gives example SIZE values, with the corresponding region size and value of N in the MPU_RBAR.