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4.5.5. MPU Region Attribute and Size Register

The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. See the register summary in Table 4.25 for its attributes.

The bit assignments are:

Table 4.30. MPU_RASR bit assignments
BitsNameFunction
[31:29]-Reserved.
[28]XN

Instruction access disable bit:

0 = instruction fetches enabled.1 = instruction fetches disabled.

[27]-Reserved.
[26:24]APAccess permission field, see Table 4.33.
[23:19]-Reserved.
[18]S

Shareable bit, see Table 4.32.

[17]C

Cacheable bit, see Table 4.32.

[16]B

Bufferable bit, see Table 4.32.

[15:8]SRD

Subregion disable bits. For each bit in this field:

0 = corresponding sub-region is enabled.

1 = corresponding sub-region is disabled.

See Subregions for more information.

[7:6]-Reserved.
[5:1]SIZESpecifies the size of the MPU region. The minimum permitted value is 7 (b00111). See SIZE field values for more information.
[0]ENABLERegion enable bit.[a]

[a] The region enable bit of all regions is reset to 0. This enables you to only program regions you want enabled.


For information about access permission, see MPU access permission attributes.

SIZE field values

The SIZE field defines the size of the MPU memory region specified by the MPU_RNR, as follows:

    (Region size in bytes) = 2(SIZE+1)

The smallest permitted region size is 256B, corresponding to a SIZE value of 7. Table 4.31 gives example SIZE values, with the corresponding region size and value of N in the MPU_RBAR.

Table 4.31. Example SIZE field values
SIZE valueRegion sizeValue of N [a]Note
b00111 (7)256B8Minimum permitted size.
b01001 (9)1KB10-
b10011 (19)1MB20-
b11101 (29)1GB30-
b11111 (31)4GB32Maximum possible size.

[a] In the MPU_RBAR, see MPU Region Base Address Register.


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