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4.2. Nested Vectored Interrupt Controller

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports:

  • 0 to up to 32 interrupts.

  • A programmable priority level of 0-192 in steps of 64 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest programmable interrupt priority.

  • Level and pulse detection of interrupt signals.

  • Interrupt tail-chaining.

  • An external Non-Maskable Interrupt (NMI).

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is:

Table 4.2. NVIC register summary
AddressNameType

Reset value

Description
0xE000E100NVIC_ISERRW0x00000000Interrupt Set-Enable Register.
0xE000E180NVIC_ICERRW0x00000000Interrupt Clear-Enable Register.
0xE000E200NVIC_ISPRRW0x00000000Interrupt Set-Pending Register.
0xE000E280NVIC_ICPRRW0x00000000Interrupt Clear-Pending Register.
0xE000E400-0xE000E4EFNVIC_IPR0-7RW0x00000000Interrupt Priority Registers.

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