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4.3.3. Interrupt Control and State Register

  • The ICSR provides:

    • A set-pending bit for the Non-Maskable Interrupt (NMI) exception.

    • Set-pending and clear-pending bits for the PendSV and SysTick exceptions

  • The ICSR indicates:

    • The exception number of the highest priority pending exception.

See the register summary in Table 4.9 for the ICSR attributes. The bit assignments are:

Table 4.11. ICSR bit assignments
BitsNameTypeFunction
[31]NMIPENDSETRW

NMI set-pending bit.

Write:

0 = no effect.

1 = changes NMI exception state to pending.

Read:

0 = NMI exception is not pending.

1 = NMI exception is pending.

Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.

[30:29]--Reserved.
[28]PENDSVSETRW

PendSV set-pending bit.

Write:

0 = no effect.

1 = changes PendSV exception state to pending.

Read:

0 = PendSV exception is not pending.

1 = PendSV exception is pending.

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

[27]PENDSVCLRWO

PendSV clear-pending bit.

Write:

0 = no effect1 = removes the pending state from the PendSV exception.

[26]PENDSTSETRW

SysTick exception set-pending bit.

Write:

0 = no effect.

1 = changes SysTick exception state to pending.

Read:

0 = SysTick exception is not pending.

1 = SysTick exception is pending.

[25]PENDSTCLRWO

SysTick exception clear-pending bit.

Write:

0 = no effect.

1 = removes the pending state from the SysTick exception.

This bit is WO. On a register read its value is Unknown.

[24:18]--Reserved.
[17:12]VECTPENDINGRO

Indicates the exception number of the highest priority pending enabled exception:

0 = no pending exceptions.

Nonzero = the exception number of the highest priority pending enabled exception.

Note

Subtract 16 from this value to obtain the CMSIS IRQ number that identifies the corresponding bit in the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-pending, and Priority Register, see Table 2.5.

[11:0]--Reserved.

When you write to the ICSR, the effect is Unpredictable if you:

  • Write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit.

  • Write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.

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