You copied the Doc URL to your clipboard.

3.5.3. ASR, LSL, LSR, and ROR

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.

Syntax

ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs

where:

Rd

Is the destination register. If Rd is omitted, it is assumed to take the same value as Rm.

Rm

Is the register holding the value to be shifted.

Rs

Is the register holding the shift length to apply to the value in Rm.

imm

Is the shift length. The range of shift length depends on the instruction:

ASR

shift length from 1 to 32

LSL

shift length from 0 to 31

LSR

shift length from 1 to 32.

Note

MOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.

Operation

ASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left, logical-shift-right or a right-rotation of the bits in the register Rm by the number of places specified by the immediate imm or the value in the least-significant byte of the register specified by Rs.

For details of what result is generated by the different instructions, see Shift operations.

Restrictions

In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate instructions, Rd and Rm must specify the same register.

Condition flags

These instructions update the N and Z flags according to the result.

The C flag is updated to the last bit shifted out, except when the shift length is 0, see Shift operations. The V flag is left unmodified.

Examples

    ASRS    R7, R5, #9  ; Arithmetic shift right by 9 bits
    LSLS    R1, R2, #3  ; Logical shift left by 3 bits with flag update
    LSRS    R4, R5, #6  ; Logical shift right by 6 bits
    RORS    R4, R4, R6  ; Rotate right by the value in the bottom byte of R6.
Was this page helpful? Yes No