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2.2.1. Memory regions, types and attributes

The default memory map and the programming of the optional MPU split the address space into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region.

The memory types are:


The processor can re-order transactions for efficiency, or perform speculative reads.


The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.


The processor preserves transaction order relative to all other transactions.

The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.

The additional memory attributes include.


For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller.

Strongly-ordered memory is always shareable.

If multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters.


This attribute is relevant only if the device is likely to be used in systems where memory is shared between multiple processors.

Execute Never (XN)

The processor cannot execute instructions in an XN region. A HardFault exception is generated if it tries.

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