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ARM Compiler Getting Started Guide : About ARMv8 terminology

About ARMv8 terminology

ARMv8 introduces a number of terms to describe the state of the integer register bank and supported instruction sets.

ARMv8 introduces the following terms to describe the state of the integer register bank:

AArch32
The 32-bit Execution state in which the general-purpose register bank comprises 32-bit registers. There are 16 registers (R0 to R15) available in this state, including the PC. There are additional banked registers for different Processing Element (PE) modes.
AArch64

The 64-bit Execution state in which the general-purpose register bank comprises 64-bit registers. There are 31 registers (R0 to R30) available in this state, with register number 31 being a special case.

The general-purpose registers can be accessed as either 32-bit registers or 64-bit registers. The 32-bit registers are accessed using the W registers. The 64-bit registers are accessed using the X registers. The W registers access the lower half (bits 0 to 31) of the X registers.

Register number 31 represents:

Zero Register
In most cases register number 31 reads as zero when used as a source register, and discards the result when used as a destination register.
Stack Pointer
When used as a load/store base register, and in a small selection of arithmetic instructions, register number 31 provides access to the current stack pointer.

The PC is never accessible as a named register.

ARMv8 introduces the following terms to describe the instruction sets supported:

instruction
An instruction that a processor can execute when in AArch32. When executing these instructions, the processor is in A32 state. These are 32-bit encoded instructions and must be word aligned. A32 instructions were previously called ARM instructions.
T32 instruction
An instruction that a processor can execute when in AArch32. When executing these instructions, the processor is in T32 state. These include 16-bit and 32-bit encoded instructions. These instructions must be half-word aligned. T32 instructions incorporate Thumb-2 technology. T32 instructions were previously called Thumb instructions.
A64 instruction
An instruction that a processor can execute when in AArch64. These are 32-bit encoded instructions and must be word aligned.

Note

The terms A32, T32, and AArch32 also apply to ARMv7 and ARMv6-M architectures, with the exception that the M-profile architectures do not support A32 instructions. In the context of instructions and states, the terms ARM and Thumb are the former terms for A32 and T32 respectively.

Note

Detailed information about the ARMv8 architecture is available under license. Contact your ARM Account Representative for details.