Instruction Synchronization Barrier.
is an optional condition code.
is permitted only in T32 code. This is an unconditional instruction in A32.
is an optional limitation on the operation of the hint. The permitted value is:
DMBoperation. This is the default and can be omitted.
Instruction Synchronization Barrier flushes the pipeline in
the processor, so that all instructions following the
fetched from cache or memory, after the instruction has been completed. It
ensures that the effects of context altering operations, such as
changing the ASID, or completed TLB maintenance operations, or branch
predictor maintenance operations, in addition to all changes to
the CP15 registers, executed before the
are visible to the instructions fetched after the
In addition, the
ensures that any branches that appear in program order after it are
always written into the branch prediction logic with the context
that is visible after the
This is required to ensure correct execution of the instruction
NoteWhen the target architecture is ARMv7-M, you cannot use an
ISBinstruction in an IT block, unless it is the last instruction in the block.
This 32-bit instructions are available in A32 and T32.
There is no 16-bit version of this instruction in T32.