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VTST
Vector Test bits.
Syntax
VTST{condsizeQdQnQm
VTST{condsizeDdDnDm
where:
condis an optional condition code.
sizemust be one of
8,16, or32.Qd, Qn, Qmspecifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dmspecifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
Operation
VTST takes each element in a vector, and bitwise logical ANDs them with
the corresponding element of a second vector. If the result is not zero, the corresponding
element in the destination vector is set to all ones. Otherwise, it is set to all zeros.