ADRL pseudo-instruction
Load a PC-relative or register-relative address into a register.
Syntax
ADRL
{
}
cond
,Rd
label
where:
cond
is an optional condition code.
Rd
is the register to load.
label
is a PC-relative or register-relative expression.
Usage
ADRL
always assembles to two 32-bit
instructions. Even if the address can be reached in a single instruction,
a second, redundant instruction is produced.
If the assembler cannot construct the address in two instructions,
it generates an error message and the assembly fails. You can use
the LDR
pseudo-instruction for loading
a wider range of addresses.
ADRL
is similar to the ADR
instruction, except
ADRL
can load a wider range of addresses because it generates two data
processing instructions.
ADRL
produces position-independent
code, because the address is PC-relative or register-relative.
If label
is PC-relative,
it must evaluate to an address in the same assembler area as the ADRL
pseudo-instruction.
If you use ADRL
to generate a target for a
BX
or BLX
instruction,
it is your responsibility to set the T32 bit (bit 0) of the address if the target contains
T32 instructions.
Architectures and range
The available range depends on the instruction set in use:
- A32
-
The range of the instruction is any value that can be generated by two
ADD
or twoSUB
instructions. That is, any value that can be produced by the addition of two values, each of which is 8 bits rotated right by any even number of bits within a 32-bit word. - T32, 32-bit encoding
-
±1MB bytes to a byte, halfword, or word-aligned address.
- T32, 16-bit encoding
-
ADRL
is not available.
The given range is relative to a point four bytes (in T32 code) or two words (in A32 code) after the address of the current instruction.
Note
When assembling T32 instructions,ADRL
is only available in ARMv6T2 and later.