BLX, BLXNS
Branch with Link and exchange instruction set and Branch with Link and Exchange (Non-secure).
Note
This topic includes descriptions of [BETA] features.Syntax
BLX{
cond
}{q
} label
BLX{
cond
}{q
} Rm
[BETA]
(ARMv8-M only)BLXNS{
cond
}{q
} Rm
where:
cond
- Is an optional condition code.
is not available on all forms of this instruction.cond
q
- Is an optional instruction width specifier. Must be set to
.W
whenlabel
is used. label
- Is a PC-relative expression.
Rm
- Is a register containing an address to branch to.
Operation
The BLX
instruction causes a branch to
label
, or to the address contained in
. In addition:Rm
- The
BLX
instruction copies the address of the next instruction into LR (R14
, the link register). -
The
BLX
instruction can change the instruction set.BLX
always changes the instruction set. It changes a processor in A32 state to T32 state, or a processor in T32 state to A32 state.label
BLX
derives the target instruction set from bit[0] ofRm
:Rm
- If bit[0] of
is 0, the processor changes to, or remains in, A32 state.Rm
- If bit[0] of
is 1, the processor changes to, or remains in, T32 state.Rm
- If bit[0] of
Note
- There are no equivalent instructions to
BLX
to change between AArch32 and AArch64 state. The only way to change execution state is by a change of exception level. - ARMv8-M only supports the T32 instruction set. An attempt to change the instruction execution state causes the processor to take an exception on the instruction at the target address.
The
BXNS
instruction calls a subroutine at an address and instruction set specified
by a register, and causes a transition from the Secure to the Non-secure domain. This
variant of the instruction must only be used when additional steps required to make such a
transition safe are taken.
Instruction availability and branch ranges
The following table shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.
Table 13-6 BLX instruction availability and range
Instruction | A32 | T32, 16-bit encoding | T32, 32-bit encoding |
---|---|---|---|
BLX label |
±32MB | ±4MB a | ±16MB |
BLX Rm |
Available | Available | Use 16-bit |
BLX{cond}
Rm |
Available | - | - |
BLXNS
|
- | Available | - |
Register restrictions
You can use PC for R
in the A32 m
BLX
instruction, but
this is deprecated. You cannot use PC in other A32 instructions.
You can use PC for R
in the T32 m
BLX
instruction. You
cannot use PC in other T32 instructions.
You can use SP for R
in this A32 instruction but this is deprecated.m
You can use SP for R
in the T32 m
BLX
and BLXNS
instructions, but this is deprecated. You cannot use SP in
the other T32 instructions.
Condition flags
These instructions do not change the flags.
Availability
See the preceding table for details of availability of the BLX
and BLXNS
instructions in
both instruction sets.
Related concepts
Related information
BLX label
and BL label
are an instruction pair.