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BX, BXNS

Branch and exchange instruction set and Branch and Exchange Non-secure.

Note

This topic includes descriptions of [BETA] features.

Syntax

BX{cond}{q} Rm

[BETA] BXNS{cond}{q} Rm (ARMv8-M only)

where:

cond
Is an optional condition code. cond is not available on all forms of this instruction.
q
Is an optional instruction width specifier.
Rm
Is a register containing an address to branch to.

Operation

The BX instruction causes a branch to the address contained in Rm and exchanges the instruction set, if required. The BX instruction can change the instruction set.

BX Rm derives the target instruction set from bit[0] of Rm:

  • If bit[0] of Rm is 0, the processor changes to, or remains in, A32 state.
  • If bit[0] of Rm is 1, the processor changes to, or remains in, T32 state.

Note

  • There are no equivalent instructions to BX to change between AArch32 and AArch64 state. The only way to change execution state is by a change of exception level.
  • ARMv8-M only supports the T32 instruction set. An attempt to change the instruction execution state causes the processor to take an exception on the instruction at the target address.

BX can also be used for an exception return.

[BETA] The BXNS instruction causes a branch to an address and instruction set specified by a register, andcauses a transition from the Secure to the Non-secure domain. This variant of the instruction must only be used when additional steps required to make such a transition safe are taken.

Instruction availability and branch ranges

The following table shows the instructions that are available in A32 and T32 state. Instructions that are not shown in this table are not available.

Table 13-7 BX instruction availability and range

Instruction A32 T32, 16-bit encoding T32, 32-bit encoding
BX Rm Available Available Use 16-bit
BX{cond} Rm Available - -
BXNS - Available -

Register restrictions

You can use PC for Rm in the A32 BX instruction, but this is deprecated. You cannot use PC in other A32 instructions.

You can use PC for Rm in the T32 BX and BXNS instructions. You cannot use PC in other T32 instructions.

You can use SP for Rm in the A32 BX instruction but this is deprecated in ARMv6T2 and above.

You can use SP for Rm in the T32 BX and BXNS instructions, but this is deprecated.

Condition flags

These instructions do not change the flags.

Availability

See the preceding table for details of availability of the BX and BXNS instructions in both instruction sets.

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