DMB
Data Memory Barrier.
Syntax
DMB
{
}
{cond
}
option
where:
cond
-
is an optional condition code.
Note
is permitted only in T32 code. This is an unconditional instruction in A32.cond
option
-
is an optional limitation on the operation of the hint. Permitted values are:
SY
-
Full system
DMB
operation. This is the default and can be omitted. LD
-
DMB
operation that waits only for loads to complete. ST
-
DMB
operation that waits only for stores to complete. ISH
-
DMB
operation only to the inner shareable domain. ISHLD
-
DMB
operation that waits only for loads to complete, and only applies to the inner shareable domain. ISHST
-
DMB
operation that waits only for stores to complete, and only to the inner shareable domain. NSH
-
DMB
operation only out to the point of unification. NSHLD
-
DMB
operation that waits only for loads to complete and only applies out to the point of unification. NSHST
-
DMB
operation that waits only for stores to complete and only out to the point of unification. OSH
-
DMB
operation only to the outer shareable domain. OSHLD
-
DMB
operation that waits only for loads to complete, and only applies to the outer shareable domain. OSHST
-
DMB
operation that waits only for stores to complete, and only to the outer shareable domain.
Note
The optionsLD
,
ISHLD
, NSHLD
, and OSHLD
are
supported only in ARMv8.Operation
Data Memory Barrier acts as a memory barrier. It ensures that
all explicit memory accesses that appear in program order before
the DMB
instruction are observed before
any explicit memory accesses that appear in program order after
the DMB
instruction. It does not affect
the ordering of any other instructions executing on the processor.
Alias
The following alternative values of
are
supported, but ARM recommends that you do not use them:option
- SH is an alias for ISH.
- SHST is an alias for ISHST.
- UN is an alias for NSH.
- UNST is an alias for NSHST.
Architectures
This 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.