LDR (register offset)
Load with register offset, pre-indexed register offset, or post-indexed register offset.
Syntax
LDR
{
}{type
} cond
, [Rt
, ±Rn
{, Rm
}] ; register offset shift
LDR
{
}{type
} cond
, [Rt
, ±Rn
{, Rm
}]! ; pre-indexed ;
A32 only shift
LDR
{
}{type
} cond
, [Rt
], ±Rn
{, Rm
} ; post-indexed ;
A32 only shift
LDRD
{
} cond
, Rt
, [Rt2
, ±Rn
] ; register offset,
doubleword ; A32 only Rm
LDRD
{
} cond
, Rt
, [Rt2
, ±Rn
]! ; pre-indexed,
doubleword ; A32 only Rm
LDRD
{
} cond
, Rt
, [Rt2
], ±Rn
; post-indexed,
doubleword ; A32 only Rm
where:
type
-
can be any one of:
B
-
unsigned Byte (Zero extend to 32 bits on loads.)
SB
-
signed Byte (
LDR
only. Sign extend to 32 bits.) H
-
unsigned Halfword (Zero extend to 32 bits on loads.)
SH
-
signed Halfword (
LDR
only. Sign extend to 32 bits.) -
-
omitted, for Word.
cond
-
is an optional condition code.
Rt
-
is the register to load.
Rn
-
is the register on which the memory address is based.
Rm
-
is a register containing a value to be used as the offset.
is not permitted in T32 code.-Rm
shift
-
is an optional shift.
Rt2
-
is the additional register to load for doubleword operations.
Not all options are available in every instruction set and architecture.
Offset register and shift options
The following table shows the ranges of offsets and availability of these instructions:
Table 13-12 Options and architectures, LDR (register offsets)
Instruction | +/-Rm
a
|
shift | ||
---|---|---|---|---|
A32, word or byte b | +/-
|
LSL
#0-31 |
LSR
#1-32 |
|
ASR
#1-32 |
ROR
#1-31 |
RRX |
||
A32, signed byte, halfword, or signed halfword | +/-
|
Not available | ||
A32, doubleword | +/-
|
Not available | ||
32-bit encoding, word, halfword, signed halfword, byte, or signed byte b | +
|
LSL #0-3 |
||
16-bit encoding, all except doubleword c | +
|
Not available |
Register restrictions
In the pre-index and post-index forms, R
must be different from n
R
.t
Doubleword register restrictions
For A32 instructions:
must be an even-numbered register.Rt
must not be LR.Rt
- ARM strongly recommends that you do not use
R12
for
.Rt
must beRt2
R(
.t
+ 1)R
must be different fromm
R
andt
R
int2
LDRD
instructions.R
must be different fromn
R
in the pre-index and post-index forms.t2
Use of PC
In A32 instructions you can use PC for R
in t
LDR
word
instructions, and you can use PC for R
in n
LDR
instructions with
register offset syntax (that is the forms that do not writeback to the R
).n
Other uses of PC are not permitted in A32 instructions.
In T32 instructions you can use PC for R
in t
LDR
word
instructions. Other uses of PC in these T32 instructions are not permitted.
Use of SP
You can use SP for R
. n
In A32 code, you can use SP for R
in word instructions. You can use SP for t
R
in non-word A32
instructions but this is deprecated in ARMv6T2 and above.t
You can use SP for R
in A32 instructions but this is deprecated in ARMv6T2 and
above.m
In T32 code, you can use SP for R
in word instructions only. All other use of SP for
t
R
in these
instructions are not permitted in T32 code.t
Use of SP for R
is not permitted in T32 state.m
Related concepts
Related reference
Where +/-Rm is shown, you can use -Rm, +Rm, or Rm. Where +Rm is shown, you cannot use -Rm.
For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in T32 state, otherwise execution continues in A32 state.
Rt, Rn, and Rm must all be in the range R0-R7.