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MRRC and MRRC2

Move to ARM Registers from Coprocessor. Depending on the coprocessor, you might be able to specify various additional operations.

Note

MRRC2 is not supported in ARMv8.

Syntax

MRRC{cond} coproc, #opcode, Rt, Rt2, CRm

MRRC2{cond} coproc, #opcode, Rt, Rt2, CRm

where:

cond

is an optional condition code.

In A32 code, cond is not permitted for MRRC2.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer whose value must be:

  • In the range 0-15 in ARMv7 and earlier.

  • or 15 in ARMv8.

opcode

is a 4-bit coprocessor-specific opcode.

Rt, Rt2

are ARM destination registers. Rt and Rt2 must not be PC.

CRm

is a coprocessor register.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

These 32-bit instructions are available in A32 and T32.

There are no 16-bit versions of these instructions in T32.

Related reference

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