Operation

ROR provides the value of the contents of a register rotated by a value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

Restrictions in T32 code

instructions must not use PC or SP.

Use of SP and PC in A32 instructions

You can use SP in these A32 instructions but this is deprecated.

You cannot use PC in instructions with the ROR{S}{cond} Rd, Rm, Rs syntax. You can use PC for Rd and Rm in the other syntax, but this is deprecated.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

• Execution branches to the address corresponding to the result.

• If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions.

  Note

  The A32 instruction RORS{cond} pc,Rm,#sh always disassembles to the preferred form MOVS{cond} pc,Rm{,shift}.

You cannot use PC for Rd or any operand in this instruction if it has a register-controlled shift.

Condition flags

If S is specified, the instruction updates the N and Z flags according to the result.

The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

16-bit instructions

The following forms of this instruction are available in T32 code, and are 16-bit instructions:

RORS Rd, Rd, Rs

Rd and Rs must both be Lo registers. This form can only be used outside an IT block.

ROR{cond} Rd, Rd, Rs

Rd and Rs must both be Lo registers. This form can only be used inside an IT block.

Architectures

This instruction is available in A32 and T32.

Example

    ROR     r4, r5, r6