ROR
Rotate Right. This instruction is a preferred synonym for MOV
instructions with shifted register operands.
Syntax
ROR
{S
}{
}
cond
,
Rd
,
Rm
Rs
ROR
{S
}{
}
cond
,
Rd
,
#Rm
sh
where:
S
is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
Rd
is the destination register.
Rm
is the register holding the first operand. This operand is shifted right.
Rs
is a register holding a shift value to apply to the value in
. Only the least significant byte is used.Rm
sh
is a constant shift. The range of values is 1-31.
Operation
ROR
provides the value of the contents
of a register rotated by a value. The bits that are rotated off
the right end are inserted into the vacated bit positions on the
left.
Restrictions in T32 code
instructions must not use PC or SP.
Use of SP and PC in A32 instructions
You can use SP in these A32 instructions but this is deprecated.
You cannot use PC in instructions with the ROR{S}{cond}
Rd, Rm, Rs
syntax. You can use PC for R
and d
R
in the other syntax, but this is
deprecated. m
If you use PC as Rm
, the
value used is the address of the instruction plus 8.
If you use PC as Rd
:
- Execution branches to the address corresponding to the result.
If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions.
Note
The A32 instructionRORS{
always disassembles to the preferred formcond
} pc,Rm,#shMOVS{
.cond
} pc,Rm{,shift}
Caution
Do not use the S suffix when using PC asRd
in User mode or System mode.
The assembler cannot warn you about this because it has no information about what
the processor mode is likely to be at execution time.You cannot use PC for Rd
or
any operand in this instruction if it has a register-controlled
shift.
Condition flags
If S is specified, the instruction updates the N and Z flags according to the result.
The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.
16-bit instructions
The following forms of this instruction are available in T32 code, and are 16-bit instructions:
RORS
Rd
,Rd
,Rs
andRd
must both be Lo registers. This form can only be used outside an IT block.Rs
ROR{
cond
}Rd
,Rd
,Rs
andRd
must both be Lo registers. This form can only be used inside an IT block.Rs
Architectures
This instruction is available in A32 and T32.
Example
ROR r4, r5, r6