SADD16
Signed parallel halfword-wise addition.
Syntax
SADD16
{
}
{cond
}, Rd
,
Rn
Rm
where:
cond
is an optional condition code.
Rd
is the destination register.
Rm, Rn
are the ARM registers holding the operands.
Operation
This instruction performs two signed integer additions on the corresponding halfwords of the operands and writes the results into the corresponding halfwords of the destination. The results are modulo 216. It sets the APSR GE flags.
Register restrictions
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
GE flags
This instruction does not affect the N, Z, C, V, or Q flags.
It sets the GE flags in the APSR as follows:
GE[1:0]
for bits[15:0] of the result.
GE[3:2]
for bits[31:16] of the result.
It sets a pair of GE flags to 1 to indicate that the corresponding result is greater than or
equal to zero. This is equivalent to an ADDS
instruction setting the N and
V condition flags to the same value, so that the GE condition passes.
You can use these flags to control a following SEL
instruction.
Note
GE[1:0] are set or cleared together, and GE[3:2] are set or cleared together.Availability
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.