is an optional condition code.
is the destination register.
is the register holding the value to be divided.
is a register holding the divisor.
PC or SP cannot be used for
This 32-bit T32 instruction is available in ARMv7-R and ARMv7-M.
This 32-bit A32 instruction is optional in ARMv7-R.
This 32-bit A32 and T32 instruction is available in ARMv7-A if Virtualization Extensions are implemented, and optional if not.
There is no 16-bit T32