SMLSLD
Dual 16-bit Signed Multiply with Subtraction of products and 64-bit accumulation.
Syntax
SMLSD{X}{condRdLoRdHiRnRm
where:
Xis an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.
condis an optional condition code.
RdLo,RdHiare the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand.
RdHiandRdLomust be different registers.Rn, Rmare the registers holding the operands.
Operation
SMLSLD multiplies the bottom halfword of Rn with the bottom
halfword of Rm, and the top halfword of Rn with the
top halfword of Rm. It then subtracts the second product from the first,
adds the difference to the value in RdLo, RdHi, and
stores the result to RdLo, RdHi.
Register restrictions
You cannot use PC for any operand.
You can use SP in A32 instructions but this is deprecated. You cannot use SP in T32 instructions.
Condition flags
This instruction does not change the flags.
Availability
The 32-bit instruction is available in A32 and T32.
There is no 16-bit version of this instruction in T32.
Example
SMLSLD r3, r0, r5, r1