You copied the Doc URL to your clipboard.
VBIC (register)
Vector Bit Clear.
Syntax
VBIC{conddatatypeQdQnQm
VBIC{conddatatypeDdDnDm
where:
condis an optional condition code.
datatypeis an optional data type. The assembler ignores
datatypeQd, Qn, Qmspecifies the destination register, the first operand register, and the second operand register, for a quadword operation.
Dd, Dn, Dmspecifies the destination register, the first operand register, and the second operand register, for a doubleword operation.
Operation
VBIC performs a bitwise logical AND
complement between two registers, and places the result in the destination register.