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VLDn (multiple n-element structures)

Vector Load multiple n-element structures.

Syntax

VLDn{cond}.datatype list, [Rn{@align}]{!}

VLDn{cond}.datatype list, [Rn{@align}], Rm

where:

n

must be one of 1, 2, 3, or 4.

cond

is an optional condition code.

datatype

see the following table for options.

list

is the list of Advanced SIMD registers enclosed in braces, { and }. See the following table for options.

Rn

is the ARM register containing the base address. Rn cannot be PC.

align

specifies an optional alignment. See the following table for options.

!

if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads have taken place.

Rm

is an ARM register containing an offset from the base address. If Rm is present, the instruction updates Rn to (Rn + Rm) after using the address to access memory. Rm cannot be SP or PC.

Operation

VLDn loads multiple n-element structures from memory into one or more Advanced SIMD registers, with de-interleaving (unless n == 1). Every element of each register is loaded.

Table 14-6 Permitted combinations of parameters for VLDn (multiple n-element structures)

n datatype list a align b alignment
8, 16, 32, or 64 {Dd} @64 8-byte
    {Dd, D(d+1)} @64 or @128 8-byte or 16-byte
    {Dd, D(d+1), D(d+2)} @64 8-byte
    {Dd, D(d+1), D(d+2), D(d+3)} @64, @128, or @256 8-byte, 16-byte, or 32-byte
2 8, 16, or 32 {Dd, D(d+1)} @64, @128 8-byte or 16-byte
    {Dd, D(d+2)} @64, @128 8-byte or 16-byte
    {Dd, D(d+1), D(d+2), D(d+3)} @64, @128, or @256 8-byte, 16-byte, or 32-byte
3 8, 16, or 32 {Dd, D(d+1), D(d+2)} @64 8-byte
    {Dd, D(d+2), D(d+4)} @64 8-byte
4 8, 16, or 32 {Dd, D(d+1), D(d+2), D(d+3)} @64, @128, or @256 8-byte, 16-byte, or 32-byte
    {Dd, D(d+2), D(d+4), D(d+6)} @64, @128, or @256 8-byte, 16-byte, or 32-byte

Related reference

a 

Every register in the list must be in the range D0-D31.

b 

align can be omitted. In this case, standard alignment rules apply.

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