VLDR (post-increment and pre-decrement, floating-point)
Pseudo-instruction that loads extension registers, with post-increment and pre-decrement forms.
Note
There are alsoVLDR
and VSTR
instructions
without post-increment and pre-decrement.Syntax
VLDR
{
}{.cond
}
size
, [Fd
],
#Rn
offset
; post-increment
VLDR
{
}{.cond
}
size
, [Fd
,
#-Rn
offset
]! ; pre-decrement
where:
cond
is an optional condition code.
size
is an optional data size specifier. Must be 32 if
is anFd
S
register, or 64 if
is aFd
D
register.Fd
-
is the extension register to load. It can be either a double precision (
) or a single precision (Dd
) register.Sd
Rn
is the ARM register holding the base address for the transfer.
offset
is a numeric expression that must evaluate to a numeric value at assembly time. The value must be
4
if
is anFd
S
register, or8
if
is aFd
D
register.
Operation
The post-increment instruction increments the base address
in the register by the offset value, after the transfer. The pre-decrement
instruction decrements the base address in the register by the offset
value, and then performs the transfer using the new address in the
register. This pseudo-instruction assembles to a VLDM
instruction.