Signed saturating Shift Right Unsigned Narrow (immediate).
- Is the destination width specifier, and can be one of the values shown in Usage.
- Is the number of the SIMD and FP destination register.
- Is the source width specifier, and can be one of the values shown in Usage.
- Is the number of the first SIMD and FP source register.
- Is the right shift amount, in the range 1 to the destination operand width in bits, and can be one of the values shown in Usage.
Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD and FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD and FP register. The results are truncated. For rounded results, see SQRSHRUN in the ARMv8-A Architecture Reference Manual.
SQSHRUN instruction writes the vector to the lower half of the destination register and clears the upper half, while the
SQSHRUN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 19-27 SQSHRUN (Scalar) specifier combinations
|B||H||1 to 8|
|H||S||1 to 16|
|S||D||1 to 32|