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BSL (vector)

Bitwise Select.


BSL Vd.T, Vn.T, Vm.T


Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be either 8B or 16B.
Is the name of the first SIMD and FP source register.
Is the name of the second SIMD and FP source register.


Bitwise Select. This instruction sets each bit in the destination SIMD and FP register to the corresponding bit from the first source SIMD and FP register when the original destination bit was 1, otherwise from the second source SIMD and FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

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