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FSTMDBX, FSTMIAX

FSTMX.

Syntax

FSTMDBX{c}{q} Rn!, dreglist ; A1 Decrement Before FP/SIMD registers (A32)

FSTMIAX{c}{q} Rn{!}, dreglist ; A1 Increment After FP/SIMD registers (A32)

FSTMDBX{c}{q} Rn!, dreglist ; T1 Decrement Before FP/SIMD registers (T32)

FSTMIAX{c}{q} Rn{!}, dreglist ; T1 Increment After FP/SIMD registers (T32)

Where:

c
See Standard assembler syntax fields in the ARMv8-A Architecture Reference Manual.
q
See Standard assembler syntax fields in the ARMv8-A Architecture Reference Manual.
Rn
Is the general-purpose base register. If writeback is not specified, the PC can be used. However, ARM deprecates use of the PC.
!
Specifies base register writeback.
dreglist
Is the list of consecutively numbered 64-bit SIMD and FP registers to be transferred. The list must contain at least one register, all registers must be in the range D0-D15, and must not contain more than 16 registers.

Usage

FSTMX stores multiple SIMD and FP registers from the Advanced SIMD and floating-point register file to consecutive locations in using an address from a general-purpose register.

ARM deprecates use of FLDMDBX and FLDMIAX, except for disassembly purposes, and reassembly of disassembled code.

Depending on settings in the CPACR in the ARMv8-A Architecture Reference Manual, NSACR in the ARMv8-A Architecture Reference Manual, HCPTR in the ARMv8-A Architecture Reference Manual, and FPEXC in the ARMv8-A Architecture Reference Manual registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support in the ARMv8-A Architecture Reference Manual.

Note

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors in the ARMv8-A Architecture Reference Manual.
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