Extension register load.
is an optional condition code.
is an optional data size specifier. Must be 32 if
Sregister, or 64 otherwise.
is the extension register to be loaded, and can be either a
is the ARM register holding the base address for the transfer.
is an optional numeric expression. It must evaluate to a numeric value at assembly time. The value must be a multiple of 4, and lie in the range -1020 to +1020. The value is added to the base address to form the address used for the transfer.
is a PC-relative expression.
labelmust be aligned on a word boundary within ±1KB of the current instruction.
VLDR instruction loads an extension
register from memory.
One word is transferred if
S register. Two words are
There is also a