FCVTZU (scalar, integer)
Floating-point Convert to Unsigned integer, rounding toward Zero (scalar).
Syntax
FCVTZU
Wd, Hn ; Half-precision to 32-bit
FCVTZU
Xd, Hn ; Half-precision to 64-bit
FCVTZU
Wd, Sn ; Single-precision to 32-bit
FCVTZU
Xd, Sn ; Single-precision to 64-bit
FCVTZU
Wd, Dn ; Double-precision to 32-bit
FCVTZU
Xd, Dn ; Double-precision to 64-bit
Where:
Wd- Is the 32-bit name of the general-purpose destination register.
Hn- Is the 16-bit name of the SIMD and FP source register.
Xd- Is the 64-bit name of the general-purpose destination register.
Sn- Is the 32-bit name of the SIMD and FP source register.
Dn- Is the 64-bit name of the SIMD and FP source register.
Usage
Floating-point Convert to Unsigned integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD and FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.