FNMUL (scalar)
Floating-point Multiply-Negate (scalar).
Syntax
FNMUL
Hd, Hn, Hm ; Half-precision
FNMUL
Sd, Sn, Sm ; Single-precision
FNMUL
Dd, Dn, Dm ; Double-precision
Where:
Hd- Is the 16-bit name of the SIMD and FP destination register.
Hn- Is the 16-bit name of the first SIMD and FP source register.
Hm- Is the 16-bit name of the second SIMD and FP source register.
Sd- Is the 32-bit name of the SIMD and FP destination register.
Sn- Is the 32-bit name of the first SIMD and FP source register.
Sm- Is the 32-bit name of the second SIMD and FP source register.
Dd- Is the 64-bit name of the SIMD and FP destination register.
Dn- Is the 64-bit name of the first SIMD and FP source register.
Dm- Is the 64-bit name of the second SIMD and FP source register.
Usage
Floating-point Multiply-Negate (scalar). This instruction multiplies the floating-point values of the two source SIMD and FP registers, and writes the negation of the result to the destination SIMD and FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.