SCVTF (scalar, fixed-point)
Signed fixed-point Convert to Floating-point (scalar).
Syntax
SCVTF
Hd, Wn, #fbits ; 32-bit to half-precision
SCVTF
Sd, Wn, #fbits ; 32-bit to single-precision
SCVTF
Dd, Wn, #fbits ; 32-bit to double-precision
SCVTF
Hd, Xn, #fbits ; 64-bit to half-precision
SCVTF
Sd, Xn, #fbits ; 64-bit to single-precision
SCVTF
Dd, Xn, #fbits ; 64-bit to double-precision
Where:
Hd- Is the 16-bit name of the SIMD and FP destination register.
Wn- Is the 32-bit name of the general-purpose source register.
fbits-
Depends on the instruction variant:
- 32-bit to half-precision
- For the 32-bit to double-precision, 32-bit to half-precision and 32-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32.
- 32-bit
- For the 32-bit to double-precision, 32-bit to half-precision and 32-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32.
- 64-bit to half-precision
- For the 64-bit to double-precision, 64-bit to half-precision and 64-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64.
- 64-bit
- For the 64-bit to double-precision, 64-bit to half-precision and 64-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64.
Sd- Is the 32-bit name of the SIMD and FP destination register.
Dd- Is the 64-bit name of the SIMD and FP destination register.
Xn- Is the 64-bit name of the general-purpose source register.
Usage
Signed fixed-point Convert to Floating-point (scalar). This instruction converts the signed value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD and FP destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.